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The announcement of the 350- and 400-MHz Pentium® II processors means that the current 66-MHz system bus frequency is no longer adequate. To avoid significant performance limitations due to wasted CPU cycles, it is necessary to increase the system bandwidth to 100 MHz in order to balance platform performance. The key question for designers is how to achieve this 50 percent jump in bus frequency, without resorting to exotic or expensive technologies.
The good news is that going faster does not have to be harder. The new 100-MHz system bus can be cost-effectively implemented using familiar motherboard and interconnect designs. Intel is now providing 100-MHz system bus design guidelines that will help enable PC suppliers to cost-effectively ramp new high-performance processors into performance mainstream PC products.
A new design methodology
Conventional engineering wisdom dictates that as system bus frequencies increase, the design problem becomes more difficult. Board routing restrictions become tighter, and additional effects, such as cross-talk in connectors, can occur. As the degree of difficulty increases, designers following conventional methodologies run the risk of getting caught in a repetitive loop of "route-simulate-and fix," never knowing if they are getting any closer to a final solution. Intel has developed a new design methodology that replaces the iterative method with a more straightforward approach. It is based on a technique we call "sensitivity analysis."
Sensitivity analysis is a predictive "what-if" technique that involves systematically performing thousands of hypothetical simulations to develop a profile of system behavior over all possible solutions (see Figure 1 below). Sensitivity analysis is the "Gremlin-hunter" that enables us to define a solution space that designers can use to turn predictive results into reality, avoiding "Murphy's Law" scenarios which can crop up in traditional trial and error methods.
Figure 1. Sensitivity analysis process.
System responses are compared against design specs
and mapped into a working "solution space."
For example, a designer might normally expect that trace routing for 100 MHz would be considerably more difficult than for 66 MHz. In reality, this is not the case! While a bus frequency of 66 MHz allows trace lengths of up to 7.00 inches, increasing the frequency to 100 MHz reduces the maximum allowable trace length to 6.75 inches—a reduction of only 0.25 inch. The results of Intel's sensitivity analyses are now available in the 100-MHz system bus design guidelines.
Commodity PCB solutions work
Intel's design guidelines show how commodity four-layer PCB motherboards and Slot 1 connector designs, now used for 66-MHz systems, are cost-effectively employed in 100-MHz designs. In addition, the guidelines make allowances for conditions that can be difficult to simulate, e.g. simultaneous switching output effects (SSO).
The design guidelines also spell-out the technical requirements for interconnects needed to support 100-MHz system bus designs. For example, existing 66-MHz designs incorporate termination on both the motherboard and the processor. Intel's 100-MHz design allows the motherboard termination to be removed, a technique known as single-end termination (SET). While this approach produces a cost saving, the trade-off is that design constraints are somewhat tighter, due to the shorter trace lengths required. The design guidelines allow developers to explore both approaches.
High performance—no new PCB technology required
The key message for PC platform designers is that making the move to 100 MHz does not require new PCB technology! Intel's design methodology enables the smooth, cost-effective ramping of the newest Slot 1 Pentium II processor technology into performance mainstream PCs, without significant increments in overall design cost. This is also a forward-looking design approach that anticipates future enhancements in Pentium II processor performance. Adhering to the new design guidelines is the best assurance of cost-effective, fast time-to-market implementations.
Howard Heck is a senior hardware design engineer in the Intel Architecture Lab, specializing in high-performance signaling and transmission line modeling of printed circuit board applications. He focuses on the development of high-speed system bus solutions for the Pentium II processor family.
For More Information
100-MHz System Interconnect Design Guidelines
Intel® 440BX AGPset Design Guidelines
Visit the New System Design Technology page in Platform Solutions for the latest information on a monthly basis
Intel 440BX AGPset product web site
Pentium II processor developer web site
Memory Technology news page in Platform Solutions
AGP Technology news page in Platform Solutions
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* Legal Information © 1998 Intel Corporation
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